A Time-Mode PWM 1st Order Low-Pass Filter

IF 1.6 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Journal of Low Power Electronics and Applications Pub Date : 2023-05-06 DOI:10.3390/jlpea13020032
Konstantinos P. Pagkalos, Orfeas Panetas-Felouris, S. Vlassis
{"title":"A Time-Mode PWM 1st Order Low-Pass Filter","authors":"Konstantinos P. Pagkalos, Orfeas Panetas-Felouris, S. Vlassis","doi":"10.3390/jlpea13020032","DOIUrl":null,"url":null,"abstract":"In this work, a first-order low-pass filter is proposed as suitable for time-mode PWM signal processing. In time-mode PWM signal processing, the pulse width of a rectangular pulse is the processing variable. The filter is constructed using basic time-mode building blocks such as time registers and time adders and so it is characterized by low complexity which can lead to the modular and versatile design of higher-order filters. All the building blocks of the filter were designed and verified in a TSMC 65 nm technology process. The sampling frequency was 5 MHz, the gain of the filter at low frequencies was at −0.016 dB, the cut-off frequency was 1.2323 MHz, and the power consumption was around 59.1 μW.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":1.6000,"publicationDate":"2023-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Low Power Electronics and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.3390/jlpea13020032","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

Abstract

In this work, a first-order low-pass filter is proposed as suitable for time-mode PWM signal processing. In time-mode PWM signal processing, the pulse width of a rectangular pulse is the processing variable. The filter is constructed using basic time-mode building blocks such as time registers and time adders and so it is characterized by low complexity which can lead to the modular and versatile design of higher-order filters. All the building blocks of the filter were designed and verified in a TSMC 65 nm technology process. The sampling frequency was 5 MHz, the gain of the filter at low frequencies was at −0.016 dB, the cut-off frequency was 1.2323 MHz, and the power consumption was around 59.1 μW.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
一个时间模式PWM一阶低通滤波器
本文提出了一种适用于时模PWM信号处理的一阶低通滤波器。在时模PWM信号处理中,矩形脉冲的脉宽是处理变量。该滤波器采用时间寄存器和时间加法器等基本时模构建块构建,因此具有低复杂度的特点,可以实现高阶滤波器的模块化和通用性设计。该滤波器的所有组成模块均采用台积电65nm工艺设计和验证。采样频率为5 MHz,低频增益为−0.016 dB,截止频率为1.2323 MHz,功耗约为59.1 μW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
Journal of Low Power Electronics and Applications
Journal of Low Power Electronics and Applications Engineering-Electrical and Electronic Engineering
CiteScore
3.60
自引率
14.30%
发文量
57
审稿时长
11 weeks
期刊最新文献
Understanding Timing Error Characteristics from Overclocked Systolic Multiply–Accumulate Arrays in FPGAs Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation Speed, Power and Area Optimized Monotonic Asynchronous Array Multipliers An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1