A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking

IF 3.1 4区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE ACM Transactions on Reconfigurable Technology and Systems Pub Date : 2023-04-21 DOI:10.1145/3593587
Yizhao Gao, Song Wang, Hayden Kwok-Hay So
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Abstract

Although advances in event-based machine vision algorithms have demonstrated unparalleled capabilities in performing some of the most demanding tasks, their implementations under stringent real-time and power constraints in edge systems remain a major challenge. In this work, a reconfigurable hardware-software architecture called REMOT, which performs real-time event-based multi-object tracking on FPGAs, is presented. REMOT performs vision tasks by defining a set of actions over attention units (AUs). These actions allow AUs to track an object candidate autonomously by adjusting its region of attention, and allow information gathered by each AU to be used for making algorithmic-level decisions. Taking advantage of this modular structure, algorithm-architecture codesign can be performed by implementing different parts of the algorithm in either hardware or software for different tradeoffs. Results show that REMOT can process 0.43–2.91 million events per second at 1.75–5.45 watts. Compared with the software baseline, our implementation achieves up to 44 times higher throughput and 35.4 times higher power efficiency. Migrating the Merge operation to hardware further reduces the worst-case latency to be 95 times shorter than the software baseline. By varying the AU configuration and operation, a reduction of 0.59–0.77mW per AU on the programmable logic has also been demonstrated.
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基于事件的实时多目标跟踪的可重构体系结构
尽管基于事件的机器视觉算法在执行一些最苛刻的任务方面表现出了无与伦比的能力,但它们在边缘系统中严格的实时性和功率约束下的实现仍然是一个重大挑战。在这项工作中,提出了一种称为REMOT的可重构硬件-软件架构,该架构在FPGA上执行基于事件的实时多目标跟踪。REMOT通过在注意力单位(AU)上定义一组动作来执行视觉任务。这些动作允许AU通过调整其关注区域来自主跟踪候选对象,并允许每个AU收集的信息用于做出算法级别的决策。利用这种模块化结构,可以通过在硬件或软件中实现算法的不同部分来执行算法架构的代码设计,以进行不同的权衡。结果表明,REMOT在1.75–5.45瓦的功率下每秒可处理43–291万个事件。与软件基线相比,我们的实现实现实现了高达44倍的吞吐量和35.4倍的功率效率。将合并操作迁移到硬件进一步将最坏情况下的延迟缩短到软件基线的95倍。通过改变AU的配置和操作,还证明了可编程逻辑上每个AU可减少0.59–0.77mW。
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来源期刊
ACM Transactions on Reconfigurable Technology and Systems
ACM Transactions on Reconfigurable Technology and Systems COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.90
自引率
8.70%
发文量
79
审稿时长
>12 weeks
期刊介绍: TRETS is the top journal focusing on research in, on, and with reconfigurable systems and on their underlying technology. The scope, rationale, and coverage by other journals are often limited to particular aspects of reconfigurable technology or reconfigurable systems. TRETS is a journal that covers reconfigurability in its own right. Topics that would be appropriate for TRETS would include all levels of reconfigurable system abstractions and all aspects of reconfigurable technology including platforms, programming environments and application successes that support these systems for computing or other applications. -The board and systems architectures of a reconfigurable platform. -Programming environments of reconfigurable systems, especially those designed for use with reconfigurable systems that will lead to increased programmer productivity. -Languages and compilers for reconfigurable systems. -Logic synthesis and related tools, as they relate to reconfigurable systems. -Applications on which success can be demonstrated. The underlying technology from which reconfigurable systems are developed. (Currently this technology is that of FPGAs, but research on the nature and use of follow-on technologies is appropriate for TRETS.) In considering whether a paper is suitable for TRETS, the foremost question should be whether reconfigurability has been essential to success. Topics such as architecture, programming languages, compilers, and environments, logic synthesis, and high performance applications are all suitable if the context is appropriate. For example, an architecture for an embedded application that happens to use FPGAs is not necessarily suitable for TRETS, but an architecture using FPGAs for which the reconfigurability of the FPGAs is an inherent part of the specifications (perhaps due to a need for re-use on multiple applications) would be appropriate for TRETS.
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