Asymmetric Gated Ge-Si0.7Ge0.3 nHTFET and pHTFET for Steep Subthreshold Characteristics

Abstract

The miniaturisation of transistors imposes thermal limits on MOSFET structures due to increase in leakage current and static power consumption per unit area of chip below 20 nm technology node. Tunnel FET has potential to reduce static power consumption to design below 20 nm technology within thermal limits thus increases the scope of future scaling trends. A new asymmetric Ge-Si0.7Ge0.3 hetero-junction tunnel FET (HTFET) is proposed with different oxide thickness from source and drain side. The asymmetric Ge-Si0.7Ge0.3 HTFET has steep subthreshold characteristic, low DIBL with high ION/IOFF current ratio for operating voltage less than 1V. The proposed design can be fabricated easily due to the similar lattice structure of Ge and Si. The ION/IOFF current ratio greater than 108 is achieved for gate length of 15 nm in nHTFET having Pt/HfO2 as gate contact and oxide material. The lowering of parasitic BJT effect in OFF state condition is also achieved in the same.