Validation of Proposed Test Set Reduction Hybrid Compaction Schemes for FPGA-Based Designs

Abstract

Recently, the density and intricacy of Very Large-Scale Integration (VLSI) circuits are grown, and the number of test vectors has increased drastically. Owing to this, the cost of testing is a significant component for consideration. The two main factors that measure the cost of the test are the size of the test vector sets and test data volume. Compression and compaction are the two approaches used to reduce the aforementioned factors. Compaction is a primary process in the test generation procedure, and there are two classes for it, i.e., dynamic and static compaction approaches. In this paper, the author performs testing and obtains the compact test vectors for various FPGA-based designs. The RASP-FIT fault injection testing tool provides the ATPG testing framework. In this paper, the testing is performed on various FPGA benchmark designs written in Verilog HDL, and the results are validated. The ATPG method developed under the RASP-FIT tool contains new hybrid compaction techniques that calculate compaction and fault coverage for the designs. This work is also compared with the previous work and found that the proposed compaction scheme is better at compacting the test vectors.