An Extended Range Divider Technique for Multi-Band PLL

IF 1.6 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Journal of Low Power Electronics and Applications Pub Date : 2023-07-05 DOI:10.3390/jlpea13030043
Rizwan Shaik Peerla, A. Dutta, B. Sahoo
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Abstract

This paper presents a multiplexer-based extended range multi-modulus divider (ER-MMD) technique for multi-band phase locked loop (PLL). The architecture maintains a modular structure by using conventional 2/3 divider cells and a multiplexer without adding any extra logic circuitry. The area and power overhead is minimal. The 2/3 divider cells are designed using true single phase clock (TSPC) logic for ER-MMD to operate in the sub-10 GHz range. A division range of 2 to 511 is achieved using this logic. The ER-MMD operates at a maximum frequency of 6 GHz with a worst-case current of 625 μA when powered with a 1 V supply. A dual voltage controlled oscillator (VCO), L5/S band PLL for Indian Regional Navigation Satellite System (IRNSS) application is designed, which incorporates an ER-MMD based on the proposed approach as a proof of concept. This technique achieves the best power efficiency of 12 GHz/mW, among the state-of-the-art ER-MMD designs.
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一种多波段锁相环的扩展分程技术
提出了一种基于多路复用器的多模分频器(ER-MMD)多波段锁相环技术。该架构通过使用传统的2/3分频单元和多路复用器保持模块化结构,而无需添加任何额外的逻辑电路。面积和电力开销最小。2/3分频单元采用真单相时钟(TSPC)逻辑设计,使ER-MMD在低于10 GHz的范围内工作。使用这种逻辑可以实现2到511的除法范围。当电源为1v时,ER-MMD的最大工作频率为6ghz,最坏电流为625 μA。设计了一种用于印度区域卫星导航系统(IRNSS)应用的L5/S波段双压控振荡器(VCO)锁相环,该锁相环结合了基于所提出方法的ER-MMD作为概念验证。该技术在最先进的ER-MMD设计中实现了12 GHz/mW的最佳功率效率。
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来源期刊
Journal of Low Power Electronics and Applications
Journal of Low Power Electronics and Applications Engineering-Electrical and Electronic Engineering
CiteScore
3.60
自引率
14.30%
发文量
57
审稿时长
11 weeks
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