Hardware-Implemented Lightweight Accelerator for Large Integer Polynomial Multiplication

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2023-03-10 DOI:10.1109/LCA.2023.3274931

Pengzhou He;Yazheng Tu;Çetin Kaya Koç;Jiafeng Xie

引用次数: 0

Abstract

Large integer polynomial multiplication is frequently used as a key component in post-quantum cryptography (PQC) algorithms. Following the trend that efficient hardware implementation for PQC is emphasized, in this letter, we propose a new hardware-implemented lightweight accelerator for the large integer polynomial multiplication of Saber (one of the National Institute of Standards and Technology third-round finalists). First, we provided a derivation process to obtain the algorithm for the targeted polynomial multiplication. Then, the proposed algorithm is mapped into an optimized hardware accelerator. Finally, we demonstrated the efficiency of the proposed design, e.g., this accelerator with

$v=32$

has at least 48.37% less area-delay product (ADP) than the existing designs. The outcome of this work is expected to provide useful references for efficient implementation of other PQC.

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大整数多项式乘法的硬件实现轻量级加速器

大整数多项式乘法是后量子加密(PQC)算法中经常使用的关键组件。在强调PQC的高效硬件实现的趋势下，在这封信中，我们提出了一种新的硬件实现的轻量级加速器，用于Saber(美国国家标准与技术研究院第三轮决赛选手之一)的大整数多项式乘法。首先，我们提供了一个推导过程，以获得目标多项式乘法的算法。然后，将该算法映射到优化后的硬件加速器中。最后，我们证明了所提出设计的效率，例如，$v=32$v=32的加速器比现有设计至少减少48.37%的面积延迟积(ADP)。本文的研究结果有望为其他PQC的有效实施提供有益的参考。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.