HAMMER: Hardware-Friendly Approximate Computing for Self-Attention With Mean-Redistribution And Linearization

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2023-01-04 DOI:10.1109/LCA.2022.3233832
Seonho Lee;Ranggi Hwang;Jongse Park;Minsoo Rhu
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Abstract

The recent advancement of the natural language processing (NLP) models is the result of the ever-increasing model size and datasets. Most of these modern NLP models adopt the Transformer based model architecture, whose main bottleneck is exhibited in the self-attention mechanism. As the computation required for self-attention increases rapidly as the model size gets larger, self-attentions have been the main challenge for deploying NLP models. Consequently, there are several prior works which sought to address this bottleneck, but most of them suffer from significant design overheads and additional training requirements. In this work, we propose HAMMER, hardware-friendly approximate computing solution for self-attentions employing mean-redistribution and linearization, which effectively increases the performance of self-attention mechanism with low overheads. Compared to previous state-of-the-art self-attention accelerators, HAMMER improves performance by $1.2-1.6\times$ and energy efficiency by $1.2-1.5\times$ .
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HAMMER:具有均值重分布和线性化的自注意硬件友好近似计算
自然语言处理(NLP)模型的最新进展是模型大小和数据集不断增加的结果。这些现代NLP模型大多采用基于Transformer的模型架构,其主要瓶颈表现在自注意机制上。随着模型尺寸的增大,自注意所需的计算量迅速增加,自注意一直是部署NLP模型的主要挑战。因此,之前有几项工作试图解决这一瓶颈,但其中大多数都面临着巨大的设计开销和额外的培训要求。在这项工作中,我们提出了HAMMER,这是一种采用均值再分配和线性化的自注意硬件友好近似计算解决方案,它以低开销有效地提高了自注意机制的性能。与以前最先进的自注意加速器相比,HAMMER的性能提高了1.2-1.6美元\倍1.2-1.6倍,能效提高了1.2-1.05美元\倍1.2-1.5倍。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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