A 2.3/3.3-GHz Dual Band Low Noise Amplifier Using Switchable Load Inductor in 0.18-um CMOS Technology

IF 0.2 Q4 ENGINEERING, MULTIDISCIPLINARY Makara Journal of Technology Pub Date : 2019-01-06 DOI:10.7454/MST.V22I3.3666
T. Kurniawan, Hsiao-Chin Chen
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引用次数: 1

Abstract

In this paper, the dual band low noise amplifier is designed in 0.18-μm CMOS technology. By combining the proposed switchable load inductor for gain controlling and the conventional inductive source degeneration topology, narrow band gain and good impedance matching are achieved at 2.3/3.3-GHz frequency bands. The new mathematical analysis of low noise amplifier design is derived to define the component parameters of the proposed circuits. The proposed low noise amplifier exhibits gain of 17.18 dB and 15.5 dB, and noise figure of 2.67 dB and 2.52 dB at the two frequency bands, respectively.
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采用0.18 um CMOS技术的可切换负载电感的2.3/3.3 ghz双频低噪声放大器
本文采用0.18 μm CMOS工艺设计了双波段低噪声放大器。通过将所提出的增益控制开关负载电感与传统的电感源退化拓扑相结合,在2.3/3.3 ghz频段实现了窄带增益和良好的阻抗匹配。推导了一种新的低噪声放大器设计的数学分析方法,以确定所提出电路的元件参数。所设计的低噪声放大器在两个频段的增益分别为17.18 dB和15.5 dB,噪声系数分别为2.67 dB和2.52 dB。
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来源期刊
Makara Journal of Technology
Makara Journal of Technology ENGINEERING, MULTIDISCIPLINARY-
自引率
0.00%
发文量
13
审稿时长
20 weeks
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