X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2023-07-17 DOI:10.1109/LCA.2023.3296153
Hwayong Nam;Seungmin Baek;Minbok Wi;Michael Jaemin Kim;Jaehyun Park;Chihun Song;Nam Sung Kim;Jung Ho Ahn
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引用次数: 1

Abstract

The demand for accurate information about the internal structure and characteristics of DRAM has been on the rise. Recent studies have explored the structure and characteristics of DRAM to improve processing in memory, enhance reliability, and mitigate a vulnerability known as rowhammer. However, DRAM manufacturers only disclose limited information through official documents, making it difficult to find specific information about actual DRAM devices. This paper presents reliable findings on the internal structure and characteristics of DRAM using activate-induced bitflips (AIBs), retention time test, and row-copy operation. While previous studies have attempted to understand the internal behaviors of DRAM devices, they have only shown results without identifying the causes or have analyzed DRAM modules rather than individual chips. We first uncover the size, structure, and operation of DRAM subarrays and verify our findings on the characteristics of DRAM. Then, we correct misunderstood information related to AIBs and demonstrate experimental results supporting the cause of rowhammer.
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X射线:通过发出内存命令发现DRAM内部结构和错误特征
对有关DRAM内部结构和特性的准确信息的需求一直在增长。最近的研究探索了DRAM的结构和特性,以改善内存中的处理,提高可靠性,并减轻被称为rowhammer的漏洞。然而,DRAM制造商只通过官方文件披露有限的信息,因此很难找到有关实际DRAM设备的具体信息。本文使用激活诱导位翻转(AIB)、保留时间测试和行复制操作,对DRAM的内部结构和特性进行了可靠的研究。虽然之前的研究试图了解DRAM器件的内部行为,但他们只显示了结果,没有确定原因,也没有分析DRAM模块而不是单个芯片。我们首先揭示了DRAM子阵列的大小、结构和操作,并验证了我们对DRAM特性的发现。然后,我们纠正了与AIBs相关的误解信息,并展示了支持rowhammer原因的实验结果。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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