Echo state network implementation for chaotic time series prediction

IF 1.9 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Microprocessors and Microsystems Pub Date : 2023-10-14 DOI:10.1016/j.micpro.2023.104950
Luis Gerardo de la Fraga , Brisbane Ovilla-Martínez , Esteban Tlelo-Cuautle
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Abstract

The implementation of an Echo State Neural Network (ESNN) for chaotic time series prediction is introduced. First, the ESNN is simulated using floating-point arithmetic and afterwards fixed-point arithmetic. The synthesis of the ESNN is done in a field-programmable gate array (FPGA), in which the activation function of the neurons’ outputs is a hyperbolic tangent one, and is approximated with a new design of quadratic order b-splines and four integer multipliers. The FPGA implementation of the ESNN is applied to predict four chaotic time series associated to the Lorenz, Chua, Lü, and Rossler chaotic oscillators. The experimental results show that with 50 hidden neurons, the fixed-point arithmetic is good enough when using 15 or 16 bits in the fractional part: using more bits does not reduce the mean-squared error prediction. The neurons are limited to four inputs in the hidden layer to achieve a more efficient hardware implementation, guaranteeing a prediction of more than 10 steps ahead.

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回声状态网络对混沌时间序列预测的实现
介绍了一种用于混沌时间序列预测的回声状态神经网络(ESNN)的实现。首先,使用浮点运算和定点运算对ESNN进行仿真。ESNN的合成是在现场可编程门阵列(FPGA)中完成的,其中神经元输出的激活函数是双曲正切函数,并用二阶b样条和四个整数乘法器的新设计进行近似。ESNN的FPGA实现被应用于预测与Lorenz、Chua、Lü和Rossler混沌振荡器相关的四个混沌时间序列。实验结果表明,对于50个隐藏神经元,当在小数部分使用15或16位时,定点算法就足够好了:使用更多的位不会降低均方误差预测。神经元在隐藏层中被限制为四个输入,以实现更高效的硬件实现,保证提前10步以上的预测。
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来源期刊
Microprocessors and Microsystems
Microprocessors and Microsystems 工程技术-工程:电子与电气
CiteScore
6.90
自引率
3.80%
发文量
204
审稿时长
172 days
期刊介绍: Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC). Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.
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