Luis Gerardo de la Fraga , Brisbane Ovilla-Martínez , Esteban Tlelo-Cuautle
{"title":"Echo state network implementation for chaotic time series prediction","authors":"Luis Gerardo de la Fraga , Brisbane Ovilla-Martínez , Esteban Tlelo-Cuautle","doi":"10.1016/j.micpro.2023.104950","DOIUrl":null,"url":null,"abstract":"<div><p><span>The implementation of an Echo State Neural Network (ESNN) for chaotic time series prediction is introduced. First, the ESNN is simulated using floating-point arithmetic and afterwards fixed-point arithmetic. The synthesis of the ESNN is done in a field-programmable gate array (FPGA), in which the activation function<span> of the neurons’ outputs is a hyperbolic tangent<span> one, and is approximated with a new design of quadratic order b-splines and four integer multipliers. The FPGA implementation of the ESNN is applied to predict four chaotic time series associated to the Lorenz, Chua, Lü, and Rossler chaotic oscillators. The experimental results show that with 50 hidden neurons, the fixed-point arithmetic is good enough when using 15 or 16 bits in the </span></span></span>fractional part: using more bits does not reduce the mean-squared error prediction. The neurons are limited to four inputs in the hidden layer to achieve a more efficient hardware implementation, guaranteeing a prediction of more than 10 steps ahead.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2023-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microprocessors and Microsystems","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0141933123001941","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
The implementation of an Echo State Neural Network (ESNN) for chaotic time series prediction is introduced. First, the ESNN is simulated using floating-point arithmetic and afterwards fixed-point arithmetic. The synthesis of the ESNN is done in a field-programmable gate array (FPGA), in which the activation function of the neurons’ outputs is a hyperbolic tangent one, and is approximated with a new design of quadratic order b-splines and four integer multipliers. The FPGA implementation of the ESNN is applied to predict four chaotic time series associated to the Lorenz, Chua, Lü, and Rossler chaotic oscillators. The experimental results show that with 50 hidden neurons, the fixed-point arithmetic is good enough when using 15 or 16 bits in the fractional part: using more bits does not reduce the mean-squared error prediction. The neurons are limited to four inputs in the hidden layer to achieve a more efficient hardware implementation, guaranteeing a prediction of more than 10 steps ahead.
期刊介绍:
Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC).
Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.