Balancing Performance Against Cost and Sustainability in Multi-Chip-Module GPUs

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2023-09-08 DOI:10.1109/LCA.2023.3313203

Shiqing Zhang;Mahmood Naderan-Tahan;Magnus Jahre;Lieven Eeckhout

引用次数: 0

Abstract

MCM-GPUs scale performance by integrating multiple chiplets within the same package. How to partition the aggregate compute resources across chiplets poses a fundamental trade-off in performance versus cost and sustainability. We propose the Performance Per Wafer (PPW) metric to explore this trade-off and we find that while performance is maximized with few large chiplets, and while cost and environmental footprint is minimized with many small chiplets, the optimum balance is achieved with a moderate number of medium-sized chiplets. The optimum number of chiplets depends on the workload and increases with increased inter-chiplet bandwidth.

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在多晶片模组gpu中平衡效能与成本与永续性

mcm - gpu通过在同一封装中集成多个芯片来扩展性能。如何跨小芯片划分聚合计算资源需要在性能与成本和可持续性之间进行基本权衡。我们提出了每晶圆性能(PPW)指标来探索这种权衡，我们发现，虽然使用少量大芯片可以最大化性能，同时使用许多小芯片可以最小化成本和环境足迹，但使用适量的中型芯片可以实现最佳平衡。最佳的小片数取决于工作负载，并随着小片间带宽的增加而增加。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.