Improvement of light-load efficiency using width-switching scheme for CMOS transistors

Abstract

This paper presents a derivation of the optimum width of transistors to minimize losses in monolithic CMOS buck converters. The high optimal width requires a tapered inverter chain gate driver. A technique called "width switching" is presented. It can be integrated with the inverter chain to maintain maximum converter efficiency over a wide power range, particularly at light load. Experimental results are presented from a chip containing CMOS transistors optimized for power levels between 50 mW and 200 mW. Challenges in implementing the width-switching scheme and other applications are also discussed.