A Power-and-Area Efficient $10\times 10$ Gb/s Bootstrap Transceiver in 40 nm CMOS for Referenceless and Lane-Independent Operation

Abstract

A phase interpolator (PI)-based 10 × 10 Gb/s bootstrap transceiver for referenceless and lane-independent operation is presented. PI output clock signals phase locked to the input data are used as reference clock signals for frequency locking the voltage-controlled oscillator (VCO). The VCO clock signal is then redistributed to the PIs, triggering the bootstrapping between the VCO and the PIs. All lanes operate independently as in VCO-based parallel referenceless designs while saving power and area. The measured recovered-data jitter in each lane is 0.93 psrms and the transceiver passes the OC-192 jitter-tolerance specification. A flip-chip packaged test chip is fabricated in a 40 nm CMOS technology. The test chip achieves figure-of-merits (mW/Gbps) of 2.03 and 2.13 for the receiver and the transmitter, respectively.