The Bottom Line of Complex ICs and Systems on Chip [From the EIC]

Abstract

h THIS ISSUE OF IEEE Design & Test brings to our readers a selection of highly progressive and relevant topics, focusing intently on solutions to some of today’s most challenging areas facing the design, manufacturing, and deployment of complex ICs and systems on chip. The articles highlight advances in yield improvement, design methodologies, testing, diagnosis, and temperature and power management in 3-D ICs and mixed signal circuits. I am again very pleased to present another timely issue on the fringe of our industry’s progression. By reading the articles, as I mention below, they all very much address the bottom line! This usually matters to most if not all of us! Read on! Our first article will be of interest to a broad set of constituents, from designers, to process engineers, to quality assurance personnel, and more. It comes from an international group of authors ranging from Cadence Design Systems, to UCLA and the Missouri University of Science and Technology, to Nanyang Technological University in Singapore. It is a wellknown fact that process variations in deeply scaled technologies create major design and fabrication challenges. Accurately predicting yield for analog and mixed signal circuits is equally challenging but extremely important to the success of a product and company. The article here is focused precisely on yield estimation. The authors present two distinct approaches, one that is referred to as a performance domain method, and a second referred to as a parameter domain method. The authors present a thorough analysis of the tradeoffs of these two approaches through a number of circuit examples and quantitative comparisons of the efficiency of the two different methods. The second article, by a group of Taiwanese authors, moves us back to the emerging world of 3-D ICs and yield. The authors focused their work on the integrity of interconnects in 3-D ICs, which has major impact on yield of such chips. They address design for testability, built-in self-test, and defect diagnosis and repair in 3-D ICs that are based on through silicon vias (TSVs) and interposers. The claimed improvement results are significant and should make a difference to the bottom line! Following this, Bhagavatula et al. from Purdue University present a detailed view of the issues faced in the development and implementation of real-time power sensors that may be the key to successful and cost-effective intelligent power management in highperformance ICs and systems. The authors make the point that the need for accurate on-chip estimation of load currents is critical. They present a proposed solution approach to this challenge and discuss broader issues surrounding power management. Rounding out this general-interest issue, an article by Huang and Huang from the National Tsing Hua University in Taiwan takes us back to a test and yield/binning problem with 3-D TSV ICs. The authors present the usefulness of a cell-based phaselocked loop that can be synthesized ‘‘automatically’’ to generate an on-chip clock signal reaching 1 GHz. They show how such a clock can be useful to accurately bin 3-D ICs for TSV leakage. Again, one would expect such an approach to make a difference to the bottom line. To stretch our reader’s minds and interests, a tutorial article takes us to the world of mechanical engineering, and more specifically to the world of