Design of 3D DRAM and Its Application in 3D Integrated Multi-Core Computing Systems

Abstract

This paper concerns appropriate 3D DRAM architecture design and the potential of using 3D DRAM to implement both L2 cache and main memory in 3D multi-core processor-DRAM integrated computing systems. We first present a coarse-grained 3D partitioning strategy for 3D DRAM design that can well exploit the benefits provided by 3D integration without incurring stringent constraints on through-silicon via (TSV) fabrications. Targeting multi-core processors, we further present design techniques that can effectively reduce the access latency of 3D DRAM L2 cache, hence improve the overall 3D integrated computing system performance. The effectiveness of these developed design techniques have been successfully evaluated based on CACTI-based memory modeling and full system simulations over a wide spectrum of multi-programmed workloads. Simulation results show that the proposed heterogeneous 3D DRAM design can improve the harmonic mean IPC by 23.9% on average compared with a baseline scenario using 3D DRAM only as the main memory.