Contactless Test of IC Pads, Pins, and TSVs via Standard Boundary Scan

S. Sunter, A. Roy
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引用次数: 3

Abstract

The performance of an IC's inputs and outputs (I/Os) is always specified in IC data sheets and is the performance most likely to be affected by assembly steps. As the speed and number of I/Os increase beyond low-cost ATE capabilities, and I/O pads become smaller (less than 10 microns wide for 3D assemblies), built-in self-test (BIST) of this performance becomes more attractive. This article describes a BIST that exploits relatively low-speed IEEE 1149.1 boundary scan to access the I/Os and test performance with as low as 5 ps calibrated resolution, equivalent to a bandwidth approaching 100 GHz.
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通过标准边界扫描的IC焊盘,引脚和tsv的非接触测试
集成电路输入和输出(I/ o)的性能总是在集成电路数据表中指定,并且是最可能受组装步骤影响的性能。随着I/O的速度和数量的增加超过了低成本的ATE能力,并且I/O衬垫变得更小(3D组件的宽度小于10微米),这种性能的内置自检(BIST)变得更有吸引力。本文描述了一个BIST,它利用相对低速的IEEE 1149.1边界扫描来访问I/ o,并以低至5 ps的校准分辨率(相当于接近100 GHz的带宽)测试性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Design & Test of Computers
IEEE Design & Test of Computers 工程技术-工程:电子与电气
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审稿时长
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