An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wide-band S/H

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 1989-12-01 DOI:10.1109/4.44983
M. Ishikawa;T. Tsukahara
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引用次数: 46

Abstract

An 8-b video-rate subranging analog-to-digital (A/D) converter with pipelined wideband sample-and-hold (S/H) amplifiers is described. The chip architecture is based on a newly developed subranging technique that combines a digital-to-analog subconverter and a subtractor in one body. The development of a bandwidth enhancement technique for the S/H amplifier yields a wide effective resolution bandwidth using 1- mu m CMOS technology. An effective resolution bandwidth of 25 MHz was achieved, as well as a small input capacitance of 1.5 pF, due to the high performance of the S/H circuit developed.< >
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一种具有流水线宽带S/H的8位50MHz CMOS子范围A/D转换器
介绍了一种具有流水线宽带采样保持(S/H)放大器的8b视频速率子范围模数(A/D)转换器。芯片架构基于一种新开发的子范围技术,该技术将数模子转换器和减法器结合在一个主体中。S/H放大器的带宽增强技术的发展使用1μm CMOS技术产生了宽的有效分辨率带宽。由于所开发的S/H电路的高性能,实现了25MHz的有效分辨率带宽,以及1.5pF的小输入电容>;
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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