{"title":"An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wide-band S/H","authors":"M. Ishikawa;T. Tsukahara","doi":"10.1109/4.44983","DOIUrl":null,"url":null,"abstract":"An 8-b video-rate subranging analog-to-digital (A/D) converter with pipelined wideband sample-and-hold (S/H) amplifiers is described. The chip architecture is based on a newly developed subranging technique that combines a digital-to-analog subconverter and a subtractor in one body. The development of a bandwidth enhancement technique for the S/H amplifier yields a wide effective resolution bandwidth using 1- mu m CMOS technology. An effective resolution bandwidth of 25 MHz was achieved, as well as a small input capacitance of 1.5 pF, due to the high performance of the S/H circuit developed.<\n<ETX>></ETX>","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"24 6","pages":"1485-1491"},"PeriodicalIF":5.6000,"publicationDate":"1989-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/4.44983","citationCount":"46","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/44983/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 46
Abstract
An 8-b video-rate subranging analog-to-digital (A/D) converter with pipelined wideband sample-and-hold (S/H) amplifiers is described. The chip architecture is based on a newly developed subranging technique that combines a digital-to-analog subconverter and a subtractor in one body. The development of a bandwidth enhancement technique for the S/H amplifier yields a wide effective resolution bandwidth using 1- mu m CMOS technology. An effective resolution bandwidth of 25 MHz was achieved, as well as a small input capacitance of 1.5 pF, due to the high performance of the S/H circuit developed.<
>
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.