Single-Power-Supply Six-Transistor CMOS SRAM Enabling Low-Voltage Writing, Low-Voltage Reading, and Low Standby Power Consumption

Abstract

SUMMARY We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin ( V WM ) and read margin ( V RM ) of the developed (dvlp) SRAM at a supply voltage ( V DD ) of 1 V were 0.470 and 0.1923 V, respectively. These values were 1.309 and 2.093 times V WM and V RM of the conventional (conv) SRAM, respectively. At a large threshold voltage ( V t ) variability (= +6 σ ), the minimum power supply voltage ( V Min ) for the write operation of the conv SRAM was 0.37 V, whereas it decreased to 0.22 V for the dvlp SRAM. V Min for the read operation of the conv SRAM was 1.05 V when the V t variability (= -6 σ ) was large, but the dvlp SRAM lowered it to 0.41 V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption ( P ST ) while retaining data. The measured P ST of the 2k-bit, 90-nm dvlp SRAM was only 0.957 μ W at V DD = 1.0 V, which was 9.46% of P ST of the conv SRAM (10.12 μ W). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.