{"title":"A New Electronic Tunable High-Frequency Meminductor Emulator Based on a Single VDTA","authors":"Pankaj Kumar Sharma;Sadaf Tasneem;Rajeev Kumar Ranjan","doi":"10.1109/ICJECE.2023.3261886","DOIUrl":null,"url":null,"abstract":"In this article, we have proposed an electronic tunable grounded meminductor emulator (MIE) using a single voltage difference transconductance amplifier (VDTA). Along with one VDTA, two MOSFETs and two capacitors are used in the proposed MIE. Overall, the proposed MIE requires only 18 MOS transistors and two grounded capacitors. The performance of the proposed MIE was validated using Cadence Virtuoso with a 180-nm CMOS library. The layout area of the emulator is only 1081 \n<inline-formula> <tex-math>$\\mu \\text{m}^{2}$ </tex-math></inline-formula>\n. The proposed design operates up to 25 MHz. To validate the theoretical and simulation results, an experiment was performed using CA3080 ICs and experimental results validate the simulated result. The power consumption of the proposed design is 5.93 mW.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"46 2","pages":"179-184"},"PeriodicalIF":2.1000,"publicationDate":"2023-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Canadian Journal of Electrical and Computer Engineering","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10143652/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
In this article, we have proposed an electronic tunable grounded meminductor emulator (MIE) using a single voltage difference transconductance amplifier (VDTA). Along with one VDTA, two MOSFETs and two capacitors are used in the proposed MIE. Overall, the proposed MIE requires only 18 MOS transistors and two grounded capacitors. The performance of the proposed MIE was validated using Cadence Virtuoso with a 180-nm CMOS library. The layout area of the emulator is only 1081
$\mu \text{m}^{2}$
. The proposed design operates up to 25 MHz. To validate the theoretical and simulation results, an experiment was performed using CA3080 ICs and experimental results validate the simulated result. The power consumption of the proposed design is 5.93 mW.