Early Stage DRC Prediction Using Ensemble Machine Learning Algorithms

Abstract

At leading technology nodes, the industry is facing a stiff challenge to make profitable integrated circuits (ICs). One of the primary issues is the design rule checking (DRC) violation. This research cohort with the DARPA IDEA program aims for “no-human-in-the-loop” and 24-h turnaround time to implement an IC from design specifications. In order to reduce human effort, this work introduces the ensemble random forest, gradient boosting, and Adaboost algorithms to predict DRC violations before detailed routing, which is considered the most time-consuming step in an IC design flow. In addition, this work identifies the features that critically impact DRC violations. The proposed algorithm has a 2% better F1-score compared to the existing support-vector machine (SVM) classifiers. The proposed ensemble approach has up to an area-under-the-curve–receiver operating characteristics (AUC–ROC) curve mean of 0.940 with ± 0.011 standard deviation compared to the state-of-the-art SVM classifier with an AUC–ROC curve mean of 0.854 with ± 0.01 standard deviation. The proposed ensemble approach exhibits up to 28.7% better DRC violation prediction rate compared to those using SVM algorithms on the test data. In addition, the proposed gradient boosting algorithm requires $37.5\times $ lower average training time and $50\times $ lower average testing time compared to the existing SVM methodologies.