M. Madhu Shobini;D. Prince Winston;S. Satheesh Kumar;M. Pravin;A. G. Aakash;B. Gurukarthik Babu
{"title":"S-Connected Ladder Fashion Multilevel Topology With Reduced Device Count","authors":"M. Madhu Shobini;D. Prince Winston;S. Satheesh Kumar;M. Pravin;A. G. Aakash;B. Gurukarthik Babu","doi":"10.1109/ICJECE.2022.3178177","DOIUrl":null,"url":null,"abstract":"Advancements in the field of multilevel converters (MLCs) recently have contributed to diverse electrical field applications such as electric vehicles, hybrid energy storage system, and smart grid. In the earlier stages of the basic MLC structure, a large number of switching devices were employed to obtain the replica of the sine wave. This article focuses on reducing the count of switching devices to half the quantity for a higher number of levels in the MLC structure. Proportionally, overall cost and operational complexity in power semiconductor switches get reduced remarkably providing stable operation. In this article, a new topology has been implemented from the knowledge of conventional converters and existing MLCs derived from literature. The proposed topology is designed with a reduced number of both switching devices and dc sources compared to the existing hybrid type and conventional converter structures. Its corresponding topology and mode of operations during each level are studied and the performances are also analyzed. Switching components’ requirement, switching state table and voltage stress, and total harmonic distortion (THD) values of the proposed topology were evaluated. The output five-level voltage has been generated using both MATLAB simulation and hardware experimental setup. The proposed topology with reduced device components exhibits its superior characteristics in all aspects.","PeriodicalId":100619,"journal":{"name":"IEEE Canadian Journal of Electrical and Computer Engineering","volume":"45 3","pages":"285-292"},"PeriodicalIF":2.1000,"publicationDate":"2022-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Canadian Journal of Electrical and Computer Engineering","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/9866588/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 1
Abstract
Advancements in the field of multilevel converters (MLCs) recently have contributed to diverse electrical field applications such as electric vehicles, hybrid energy storage system, and smart grid. In the earlier stages of the basic MLC structure, a large number of switching devices were employed to obtain the replica of the sine wave. This article focuses on reducing the count of switching devices to half the quantity for a higher number of levels in the MLC structure. Proportionally, overall cost and operational complexity in power semiconductor switches get reduced remarkably providing stable operation. In this article, a new topology has been implemented from the knowledge of conventional converters and existing MLCs derived from literature. The proposed topology is designed with a reduced number of both switching devices and dc sources compared to the existing hybrid type and conventional converter structures. Its corresponding topology and mode of operations during each level are studied and the performances are also analyzed. Switching components’ requirement, switching state table and voltage stress, and total harmonic distortion (THD) values of the proposed topology were evaluated. The output five-level voltage has been generated using both MATLAB simulation and hardware experimental setup. The proposed topology with reduced device components exhibits its superior characteristics in all aspects.