Optimized vedic multiplier using low power 13T hybrid full adder

Abstract

The research paper detects a modified version of the Vedic multiplier by using the sutras of Vedic mathematics by implementing a 13T hybrid full adder. A conventional multiplier is considered for comparative analysis of existing Vedic versions and a modified Vedic multiplier that better reflects the timing and usage of the device. This technology was developed and implemented by EDA. The proposed 13T hybrid full adder is achieved to reduce the static power consumption by 12.12 % and dynamic power consumption by 15.7%. The modified Vedic multiplier is implemented by using a 13T hybrid full adder which is achieved to reduce the power consumption by 10.08% and delay by 2.068%. The circuit and simulation are executed for 4-bit multiplication and can be performed in Eight-bit, Sixteen-bit or Thirty-two-bit. Results of simulation are shown only in the Vedic 4-bit multiplication technique. The results of this multiplication method are compared with existing techniques of Vedic multiplicative circuits.