Low-Latency, Small-Area FPGA Implementation of the Advanced Encryption Standard Algorithm

Abstract

This paper presents a Field-Programmable Gate Array (FPGA) implementation of an Advanced Encryption Standard (AES) algorithm using approach of combination iterative looping and Look-Up Table (LUT)-based S-box with block and key size of 128 bits. Modifications in the way of loading data out in AES encryption/decryption, loading key_expansion in Key_Expansion blocks are also proposed. The design is tested with the sample vectors provided by Federal Information Processing Standard (FIPS) 197. The design is implemented on APEX20KC Altera’s FPGA and on Virtex XCV600 Xilinx’s FPGA. For all the authors’ proposals, they are found to be very simple in FPGA-based architecture implementation, better in low latency, and small area, but large in memory, moderate throughput.