Adaptive Decision Feedback Equalization for Multi-Gbps Serial Links:Challenges and Opportunities

Abstract

This editorial briefly examines challenges in design of adaptive decision feedback equalizers for multi-Gbps serial links. The state-of-the-art of serial links over wire channels is briefly reviewed. The impairment of wire channels at high frequencies and their effect on the performance of serial links are examined. It is followed with a close examination of channel equalization techniques to combat inter-symbol interference. Challenges and opportunities in design of adaptive feedback equalizers including timing constraints, power consumption, adaptive references for error generation and thresholds for logic state determination, data-DFE, eye-opening monitor DFE, and edge-DFE, floating tap DFE are examined.