Design and Analysis of Two Low Power SRAM Cell Structures

Abstract

This article introduces the two cells of static SRAMS to mitigate static power scattering induced by entry and sub-edge leakage flows. To reduce the door spillage current, the main cell structure employs PMOS pass semiconductors. To prevent sub edge spillage while preserving execution awareness, this design uses two fold breaking point voltage generation with forward body biassing. The succeeding cell shape lowers the entrance voltages for the NMOS pass semiconductors, lowering the door spillage current as a result. Contrasted with a customary SRAM cell, the main cell structure complete power scattering by 0.492mW and current by iddmax=1.661mA.while the subsequent cell structure decreases the all out power dispersal by 0.189mW and current by iddmax=0.488mA.