A 4b 40 Gbps 140 mW 2.2 mm2 0.13 μm pipelined ADC for I-UWB receiver

Abstract

This paper proposes a 4b 40 Gbps 140 mW 2.2 mm2 0.13 μm Pipelined ADC for Impulse-UWB receiver. The proposed Pipelined ADC uses a high speed 1-bit comparator, wide band operational amplifier, sampling circuit and a high speed buffer. The individual blocks are designed using 0.130 μm CMOS low power library cells and are designed to operate at a frequency greater than 40 Gbps sampling rate. To operate at higher frequencies, specific new design techniques/algorithms such as power-efficient, capacitor ratio-independent conversion scheme, a pipeline stage-scaling algorithm, a nested CMOS gain-boosting technique, an amplifier and comparator sharing technique, and the use of minimum channel-length, thin oxide transistors with clock bootstrapping and in-line switch techniques are adopted.