Half-Perimeter Wirelength Model for VLSI Analytical Placement

Abstract

Placement is a crucial stage in physical design of VLSI. At this stage, analytical placer uses half perimeter wire length (HPWL) of the circuit as an objective function to place blocks optimally within chip. Inspired by popularly used log-sum-exp (LSE) wire length model [9], absolute (ABS) wire length model [7] and weighted average (WA) wire length model [3], we propose a new smooth wire length model for HPWL, providing smooth approximations to max function. The convergence. Properties, error upper bounds of the new model are studied. The accuracy of the new model is sharper than LSE, WA and ABS wire length model. Wire length is validated by global and detail placements generated by NTU Placer [1] on ISPD 2004 benchmark suits. Experimental results show that our model provides closest approximation to HPWL than all wire length models, with an average of 2% error in total wire length.