Detecting processor hardware faults by means of automatically generated virtual duplex systems

Abstract

A virtual duplex system (VDS) can be used to increase safety without the use of structural redundancy on a single machine. If a deterministic program P is calculating a given function f, then a VDS contains two variants P/sub a/ and P/sub b/ of P which are calculating the diverse functions f/sub a/ and f/sub b/ in sequence. If no error occurs in the process of designing and executing P/sub a/ and P/sub b/, then f= f/sub a/=f/sub b/ holds. A fault in the underlying processor hardware is likely to be detected by the deviation of the results, i.e. f/sub a/(i)/spl ne/f/sub b/(i) for input i. Normally, VDSs are generated by manually applying different diversity techniques. This paper, in contrast, presents a new method and a tool for the automated generation of VDSs with a high detection probability for hardware faults. Moreover, for the first time the diversity techniques are selected by an optimization algorithm rather than chosen intuitively. The generated VDSs are investigated extensively by means of software implemented processor fault injection.