Design of an automatic voltage regulator based on symmetric root locus technique

Abstract

An automatic voltage regulator (AVR) design based on symmetric root locus (SRL) technique for a synchronous machine infinite bus (SMIB) power system is presented. The SRL technique is used to minimise the amplifier saturation by placing the closed-loop poles (CLPs) of the system at desired locations. The desired CLPs are decided by considering the dominant pole locations that provide maximum damping on the SRL plot. The design incorporates an extended estimator to deal with uncertainties introduced due to variations of parameters or operating conditions. They reconstruct the state information including the state of disturbance dynamics simultaneous to implement full state feedback and using the reconstructed disturbance estimate to compensate the effect of external disturbance or parameter uncertainties. The performance of the system is analysed through simulating at different operating conditions. The control method improves the tracking response and provides zero estimation error in the steady-state. Illustrative examples have been provided to demonstrate the effectiveness of the developed methodology.