Power Consumption Prediction of Digital Circuits using Machine Learning

Abstract

The demand for Integrated Circuits (ICs) is increasing exponentially, leading to the challenges of a more reliable and effective Electronic Design Tool (EDA) for the circuit design flow. To overcome such limitations Machine Learning (ML) is used, which can learn from the previous design data and can apply it to the unknown design given to it. In this context, the paper proposes the use of the regression technique of ML to estimate the power consumption of the MOSFET-based digital circuits. For this purpose, to train the ML-based regressor model, a dataset is created from the PMOS based Resistive Load Inverter (RLI), NMOS based RLI, and CMOS-based NAND gate layout. For the formation of the dataset, a 90nm MOS technology node is used and it inculcates the features like capacitance, resistance, number of MOSFET, their respective width and length, and the average power consumption of the respective layout. The regressor model used to predict the power consumption in this work is linear regressor, polynomial regressor, random forest regressor, decision tree regressor, and the extra tree regressor. At last, from the experimental results, it is observed that the extra tree regressor performs better for the RLI circuits with the MSE value of $4.02\times 10^{-10}$ and $\mathrm{R}^{2}$ value of 0.61, and for the NAND gate, the polynomial linear regressor excels with the MSE value of $7.27\times 10^{-10}$ and $\mathrm{R}^{2}$ value of 0.65.