Omar I. Khan, M. Bushnell, Suresh Kumar Devanathan, V. Agrawal
{"title":"SPARTAN: a spectral and information theoretic approach to partial-scan","authors":"Omar I. Khan, M. Bushnell, Suresh Kumar Devanathan, V. Agrawal","doi":"10.1109/TEST.2007.4437620","DOIUrl":null,"url":null,"abstract":"We propose a new partial-scan algorithm, the first to use toggling rates of the flip-flops (analyzed using DSP methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. This improves the testability of the circuit-under-test (CUT). Entropy is maximized throughout the circuit to maximize the information flow (the principle of maximum entropy), which improves testability. We propose using partial-scan for testing, to maximize fault coverage (FC), reduce test volume (TV), reduce test application time (TAT), and reduce test power (TP) but we allow for full-scan during silicon debug. Full-scan is commonly used for testing, to reduce sequential automatic test-pattern generation (ATPG) to the complexity of combinational ATPG, but comes with serious TV, TAT, and TP overheads. Partial-scan significantly reduces circuit delay, when compared to full-scan, because critical flip-flops in the circuit data path do not have the extra hardware for full-scan, and therefore are roughly 5% faster, and use 10% less area. This is particularly critical for microprocessors. The HITEC ATPG program generated results for this new partial-scan algorithm.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2007.4437620","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
We propose a new partial-scan algorithm, the first to use toggling rates of the flip-flops (analyzed using DSP methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. This improves the testability of the circuit-under-test (CUT). Entropy is maximized throughout the circuit to maximize the information flow (the principle of maximum entropy), which improves testability. We propose using partial-scan for testing, to maximize fault coverage (FC), reduce test volume (TV), reduce test application time (TAT), and reduce test power (TP) but we allow for full-scan during silicon debug. Full-scan is commonly used for testing, to reduce sequential automatic test-pattern generation (ATPG) to the complexity of combinational ATPG, but comes with serious TV, TAT, and TP overheads. Partial-scan significantly reduces circuit delay, when compared to full-scan, because critical flip-flops in the circuit data path do not have the extra hardware for full-scan, and therefore are roughly 5% faster, and use 10% less area. This is particularly critical for microprocessors. The HITEC ATPG program generated results for this new partial-scan algorithm.