Considerations in the design of a high speed decimal unit

Abstract

New applications and new technologies will make high speed decimal arithmetic an attractive alternative to binary arithmetic. This new environment will be characterized by fewer computations for each item of data. Emphasis on binary arithmetic has resulted in techniques permitting great improvements in performance. Similar improvements are needed for decimal. Various forms of LSI arrays will permit new approaches to implementing arithmetic units. ROM arrays used as complex logic blocks permit practical designs of simultaneous multipliers and batch adders, with essentially the same cost and performance for BCD operands as for binary operands of the same word size.