PARCIS: a robust parallel VLSI circuit simulator

Abstract

The accurate verification of VLSI circuits is essential for their successful and economic production but is an extremely time consuming process for the large circuits of today. This paper describes a robust parallel circuit simulator, PARCIS, designed for a message passing multiprocessing system. It uses a demand driven technique, based on the analysis of hierarchically partitioned circuits. The computation time is reduced by decoupling the circuit equations and distributing the computational load over many processors. On each processor, the circuit blocks, compacted in hierarchical levels, are analyzed asynchronously according to their temporal activity. Currently the PARCIS system is running on a network of transputers. To demonstrate the effectiveness of the proposed simulation program, results are presented for the simulation of typical digital circuits, showing that the execution time decreases in a constant rate as the number of processors (transputers) increases.