Implementation of the corrector of I&Q errors in coherent processor with DSP

Abstract

Modern radars are mostly dependent upon coherent digital signal processing. This paper describes the implementation of a corrector of in-phase and quadrature errors in a coherent processor. The correcting network consists of a combination logic circuit and it can correct the gain and phase imbalances and the bias errors of the in-phase and quadrature channels in coherent signal processing. The correcting coefficients are computed with DSP using a test signal. The image level without correction is about -30 dB if the errors of gain and phase in the coherent processor are 0.5 dB and 1 degree respectively. The experimental results show that the image level is reduced to -50 dB from -30 dB after correcting the errors.