A. Wiberg, E. Myslivets, R. Nissim, A. Danicic, D. Blessing, B. Kuo, S. Radic
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引用次数: 6
Abstract
A linearized parametric sampling gate was constructed to explore its performance limits in an analog-to-digital conversion (ADC) architecture. Linear response of the sampling gate can be achieved both in high-resolution and high-rate ADC.
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