End-to-end performance forecasting: finding bottlenecks before they happen

A. Saidi, N. Binkert, S. Reinhardt, T. Mudge
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引用次数: 10

Abstract

Many important workloads today, such as web-hosted services, are limited not by processor core performance but by interactions among the cores, the memory system, I/O devices, and the complex software layers that tie these components together. Architects designing future systems for these workloads are challenged to identify performance bottlenecks because, as in any concurrent system, overheads in one component may be hidden due to overlap with other operations. These overlaps span the user/kernel and software/hardware boundaries, making traditional performance analysis techniques inadequate. We present a methodology for identifying end-to-end critical paths across software and simulated hardware in complex networked systems. By modeling systems as collections of state machines interacting via queues, we can trace critical paths through multiplexed processing engines, identify when resources create bottlenecks (including abstract resources such as flow-control credits), and predict the benefit of eliminating bottlenecks by increasing hardware speeds or expanding available resources. We implement our technique in a full-system simulator and analyze a TCP microbenchmark, a web server, the Linux TCP/IP stack, and an Ethernet controller. From a single run of the microbenchmark, our tool--within minutes--correctly identifies a series of bottlenecks, and predicts the performance of hypothetical systems in which these bottlenecks are successively eliminated, culminating in a total speedup of 3X.We then validate these predictions through hours of additional simulation, and find them to be accurate within 1--17%. We also analyze the web server, find it to be CPU-bound, and predict the performance of a system with an additional core within 6%.
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端到端性能预测:在瓶颈发生之前发现瓶颈
如今,许多重要的工作负载(如web托管服务)不是受到处理器核心性能的限制,而是受到核心、内存系统、I/O设备以及将这些组件连接在一起的复杂软件层之间的交互的限制。为这些工作负载设计未来系统的架构师面临着识别性能瓶颈的挑战,因为在任何并发系统中,由于与其他操作重叠,一个组件中的开销可能会被隐藏起来。这些重叠跨越了用户/内核和软件/硬件的边界,使得传统的性能分析技术不够充分。我们提出了一种在复杂网络系统中识别跨软件和模拟硬件的端到端关键路径的方法。通过将系统建模为通过队列交互的状态机集合,我们可以通过多路处理引擎跟踪关键路径,确定资源何时产生瓶颈(包括流控制信用等抽象资源),并通过提高硬件速度或扩展可用资源来预测消除瓶颈的好处。我们在一个全系统模拟器中实现了我们的技术,并分析了一个TCP微基准测试、一个web服务器、Linux TCP/IP堆栈和一个以太网控制器。通过一次微基准测试,我们的工具在几分钟内就能正确地识别出一系列瓶颈,并预测出这些瓶颈被逐步消除的假设系统的性能,最终使总速度提高3倍。然后,我们通过数小时的额外模拟来验证这些预测,并发现它们的准确率在1- 17%之间。我们还分析了web服务器,发现它是cpu限制的,并预测在6%的范围内增加一个额外核心的系统的性能。
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ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18 - 22, 2022 Special-purpose and future architectures Computer memory systems Basics of the central processing unit FRONT MATTER
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