Copper wires for high speed logic LSI prepared by low pressure long throw sputtering method : Special issue on materials-related issues for Cu interconnects used in ultra high speed large scaled integrated Si devices
T. Saito, T. Hashimoto, N. Ohashi, T. Fujiwara, H. Yamaguchi
{"title":"Copper wires for high speed logic LSI prepared by low pressure long throw sputtering method : Special issue on materials-related issues for Cu interconnects used in ultra high speed large scaled integrated Si devices","authors":"T. Saito, T. Hashimoto, N. Ohashi, T. Fujiwara, H. Yamaguchi","doi":"10.2320/MATERTRANS.43.1599","DOIUrl":null,"url":null,"abstract":"Copper sputtering method for fabrication of high performance logic LSI was studied. Extension of target to substrate distance is effective to improve step coverage of sputtered film combined with reduced operation pressure. Step coverage of low pressure long throw sputtering method also strongly depends upon the feature size of trenches and holes which are formed on silicon wafer. Sub-micron holes and trenches are successfully filled with copper by using this sputtering process followed by re-flow annealing process. Hydrogen annealing process prior to the sputtering deposition on via openings is also investigated to realize good conductivity through the via. This process results in the reduction of copper oxide at the surface of copper film. Using these newly developed processes, 0.2μm node BiCMOS LSI with 4 level copper interconnects was successfully fabricated and high performance of the copper interconnect system was clearly demonstrated.","PeriodicalId":18264,"journal":{"name":"Materials Transactions Jim","volume":"40 1","pages":"1599-1604"},"PeriodicalIF":0.0000,"publicationDate":"2002-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Materials Transactions Jim","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.2320/MATERTRANS.43.1599","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Copper sputtering method for fabrication of high performance logic LSI was studied. Extension of target to substrate distance is effective to improve step coverage of sputtered film combined with reduced operation pressure. Step coverage of low pressure long throw sputtering method also strongly depends upon the feature size of trenches and holes which are formed on silicon wafer. Sub-micron holes and trenches are successfully filled with copper by using this sputtering process followed by re-flow annealing process. Hydrogen annealing process prior to the sputtering deposition on via openings is also investigated to realize good conductivity through the via. This process results in the reduction of copper oxide at the surface of copper film. Using these newly developed processes, 0.2μm node BiCMOS LSI with 4 level copper interconnects was successfully fabricated and high performance of the copper interconnect system was clearly demonstrated.