The case for analyzing system level failures using structural patterns

Abstract

In the hyper-competitive consumer mobile product space where aggressive schedules, mass volume, and short life-cycles are the norm, system-level testing (SLT) plays a key role in achieving time-to-market (TTM) goals. But SLT also impedes time-to-volume (TTV) and cuts into profit margins. This talk will describe our recent experimental research to establish links between post-silicon SLT failures and production structural patterns. Operating on-chip-clocked scan patterns under non-destructive stress conditions to force incorrect responses from all devices, we apply machine learning to discern SLT failure signatures in noisy scan output data. One goal of the work is to significantly reduce SLT effort and cost, thus achieving early TTV and increased profitability. Other possibilities include diagnosis to identify systematically vulnerable regions of the design for selective test targeting with more through patterns.