A 1.5-V 14-bit CMOS DAC with a new self-calibration technique for wireless communication systems

Abstract

A 14-bit 1.5 V CMOS current steering digital to analog converter (DAC) with a new calibration technique is presented. This technique is suitable for low voltage applications and does not require digital computation and correction circuits and additional calibration DAC. The circuit has been designed and simulated in a standard 0.18 /spl mu/m CMOS technology. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are better than 0.35 LSB and 0.15 LSB, respectively. The power consumption of analog circuits is 33 mW, whereas the digital part consumes 48 mW.