Design and Evaluation of a Network-Based Asynchronous Architecture for Cryptographic Devices

Abstract

This paper presents a network-based asynchronous architecture that improves the physical-level security of cryptographic devices to known side-channel attacks. This is achieved by decorrelating power consumption measurements by exploiting parallel execution and randomised data-forwarding over a network of functional units. Instructions execute in parallel and forward register values between them, thereby avoiding the register bank. A secret-sharing scheme is used in data-forwarding to remove the effect of sending critical register values through the network, which does not significantly degrade performance and has a positive effect of increasing the noise due to network activity. The simulation results show that both the security threshold and the performance are improved, and the network-based architecture is more robust to differential power analysis when compared to the asynchronous pipelined architecture.