Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation

Abstract

Although on-product clock generation (OPCG) has been used for many years, often in conjunction with logic and memory BIST, it has usually been a very manual process to identify the cut-points and the OPCG behavior to ATPG tools so they can avoid dealing directly with the OPCG logic. To support programmable OPCG logic in an ASIC methodology flow required us to find a way to automate the handling of the OPCG logic and the various clocking sequences it can produce. This paper describes how we provide a means for dealing with the programmable aspects of OPCG for use during ATPG and shows some results.