{"title":"The light at the end of the CMOS tunnel","authors":"S. Nassif","doi":"10.1109/ASAP.2010.5540756","DOIUrl":null,"url":null,"abstract":"In spite of numerous predictions to the contrary, Silicon technology is marching along past the 22nm node and on to ever finer dimensions. Innovations at the technology device, circuit and system levels continue to enable us to scale in spite of what sometime appear to be insurmountable problems in power, lack of performance, manufacturability and so on. To a large degree, these innovations are necessary because no substitute technology has been found as yet and, in fact, it does not appear likely that any such technology will become practical this decade. This leaves us with the need to anticipate and predict the near and medium term futures of CMOS for the next handful of technology nodes. This talk will focus on doing just that, and will show how an important new constraint on future system scaling is circuit resilience. Resilience is the ability of circuits to operate in spite of challenges like noise, difficult environmental conditions, ageing and manufacturing imperfections. These factors conspire to cause transient or permanent errors that are indistinguishable from traditional \"hard\" faults typically caused by defects during fabrication. Without significant innovation at the circuit and system levels, the probability of these events can rise quite dramatically. In the area of SRAM, such phenomena have existed for the last three or four technology nodes, but significant investments in this area have indeed allowed continued system level scaling with ever larger on-chip memories. As these same phenomena start attacking integrated circuits more pervasively, there is an urgent need for research and development in this area to avert the problems certain to arise with increased defect rates. This keynote paper explores the link between the old subject of manufacturing variability and its well-known impact on circuit performance, and the new subject of the way that same variability -in the extreme- can cause complete circuit failure. With care, we will find that the light at the end of the CMOS tunnel is the opening of new opportunities to enrich CMOS with new technologies like MEMS, optics, sensors and even biological devices. Otherwise, that light is likely to be another train…","PeriodicalId":6642,"journal":{"name":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","volume":"9 1","pages":"4-9"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASAP.2010.5540756","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

Abstract

In spite of numerous predictions to the contrary, Silicon technology is marching along past the 22nm node and on to ever finer dimensions. Innovations at the technology device, circuit and system levels continue to enable us to scale in spite of what sometime appear to be insurmountable problems in power, lack of performance, manufacturability and so on. To a large degree, these innovations are necessary because no substitute technology has been found as yet and, in fact, it does not appear likely that any such technology will become practical this decade. This leaves us with the need to anticipate and predict the near and medium term futures of CMOS for the next handful of technology nodes. This talk will focus on doing just that, and will show how an important new constraint on future system scaling is circuit resilience. Resilience is the ability of circuits to operate in spite of challenges like noise, difficult environmental conditions, ageing and manufacturing imperfections. These factors conspire to cause transient or permanent errors that are indistinguishable from traditional "hard" faults typically caused by defects during fabrication. Without significant innovation at the circuit and system levels, the probability of these events can rise quite dramatically. In the area of SRAM, such phenomena have existed for the last three or four technology nodes, but significant investments in this area have indeed allowed continued system level scaling with ever larger on-chip memories. As these same phenomena start attacking integrated circuits more pervasively, there is an urgent need for research and development in this area to avert the problems certain to arise with increased defect rates. This keynote paper explores the link between the old subject of manufacturing variability and its well-known impact on circuit performance, and the new subject of the way that same variability -in the extreme- can cause complete circuit failure. With care, we will find that the light at the end of the CMOS tunnel is the opening of new opportunities to enrich CMOS with new technologies like MEMS, optics, sensors and even biological devices. Otherwise, that light is likely to be another train…
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CMOS隧道尽头的光
尽管有许多相反的预测,但硅技术正沿着22纳米节点前进,并向更精细的尺寸迈进。技术设备、电路和系统层面的创新继续使我们能够扩大规模,尽管有时在功率、性能缺乏、可制造性等方面似乎是无法克服的问题。在很大程度上,这些创新是必要的,因为到目前为止还没有找到替代技术,事实上,在这个十年里,任何这样的技术都不太可能变得实用。这让我们需要预测和预测下一批技术节点的CMOS近期和中期未来。这次演讲将集中在这一点上,并将展示未来系统扩展的一个重要的新约束是电路弹性。弹性是电路在噪声、恶劣环境条件、老化和制造缺陷等挑战下运行的能力。这些因素共同导致暂时性或永久性错误,这些错误与传统的“硬”错误难以区分,这些错误通常是由制造过程中的缺陷引起的。如果在电路和系统层面没有重大的创新,这些事件发生的可能性就会急剧上升。在SRAM领域,这种现象在过去的三四个技术节点中已经存在,但在该领域的重大投资确实允许持续的系统级扩展与更大的片上存储器。由于这些相同的现象开始越来越普遍地攻击集成电路,因此迫切需要在这一领域进行研究和开发,以避免由于缺陷率增加而必然出现的问题。这篇主题论文探讨了制造可变性的旧主题和它对电路性能的众所周知的影响之间的联系,以及同样的可变性在极端情况下可能导致完全电路故障的新主题。仔细观察,我们会发现CMOS隧道尽头的光是利用MEMS,光学,传感器甚至生物器件等新技术丰富CMOS的新机会。否则,那盏灯很可能是另一列火车……
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