Clock Period Constrained Minimal Buffer Insertion In Clock Trees

Abstract

In this paper we investigate the problem of computing a lower bound on the number of buffers required when given a maximum clock frequency and a predefined clock tree. Using generalized properties of published CMOS timing models, we formulate a novel non-linear and a simplified linear buffer insertion problem. We solve the latter optimally with an O(n) algorithm. The basic formulation and algorithm are extended to include a skew upper bound constraint. Using these algorithms we propose further algorithmic extensions that allow area and phase delay tradeoffs. Our results are verified using SPICE3e2 simulations with MCNC MOSIS 2.0μ models and parameters. Experiments show our buffer insertion algorithms can be used effectively for high-speed clock designs.