Architectures for Green routers

Abstract

As the Information and Communication (ICT) infrastructure continues to evolve, significant energy dissipation is incurred in the core routers. Core router performance will soon be limited by the power density. About two-thirds of the power dissipation in a router is in layer 3. Packet forwarding, classification, etc. contribute significantly to this. This talk explores architectures and algorithms for network functions including deep packet inspection and packet classification in core routers. We propose energy efficient designs to realize the “Green Internet” vision. We illustrate the performance improvements for such systems and demonstrate the suitability of FPGAs for these computations. We show that SRAM based solutions combined with FPGA based architectures lead to high throughput as well as reduced power dissipation compared with the state of the art solutions based TCAMs.