Challenges at 45nm and beyond

Dan Bailey, E. Soenen, Puneet Gupta, P. Villarrubia, S. Dhong
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Abstract

Design at 45nm technologies and below is a risky proposition because of the many design challenges involved: variability, leakage, verification complexity, poor analog device performance, etc. In this panel, experienced designers coming from different backgrounds talk about how they have overcome some of the design and CAD challenges in 45nm, what CAD challenges still exist and how the CAD community can help.
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45纳米及以上的挑战
45纳米及以下技术的设计是一个有风险的命题,因为涉及许多设计挑战:可变性、泄漏、验证复杂性、模拟器件性能差等。在这个小组中,来自不同背景的经验丰富的设计师谈论了他们如何克服45纳米的设计和CAD挑战,CAD挑战仍然存在,以及CAD社区如何提供帮助。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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