Modeling of Manufacturing of a Field-Effect Transistor to Determine Conditions to Decrease Length of Channel

Abstract

In this paper we introduce an approach to model technological process of manufacture of a field-effect heterotransistor. The modeling gives us possibility to optimize the technological process to decrease length of channel by using mechanical stress. As accompanying results of the decreasing one can find decreasing of thickness of the heterotransistors and increasing of their density, which were comprised in integrated circuits.