P. Gepner, V. Gamayunov, Wieslawa Litke, L. Sauge, C. Mazauric
{"title":"Evaluation of Intel Xeon E5-2600v2 based cluster for technical computing workloads","authors":"P. Gepner, V. Gamayunov, Wieslawa Litke, L. Sauge, C. Mazauric","doi":"10.1109/HPCSim.2014.6903787","DOIUrl":null,"url":null,"abstract":"In Intel's CPU releasing model, the new Ivy Bridge is a “TICK” that follows Sandy Bridge's (“TOCK”) microarchitecture principles, however, after undergoing a die shrink it is manufactured at 22nm. It also incorporates new micro-architectural upgrades. In this paper we shall evaluate the performance of a 16 bi-socket node cluster based on this 3rd generation Intel Xeon Processor E5-2697v2 meant for server and workstation market. The new architectural improvements are assessed via High Performance Computing Challenge (HPCC) benchmarks and NAS Parallel Benchmarks (NPB) where the interconnect technology is challenged by the standard Intel® MPI Benchmark suite performance evaluator. Finally we tested performance of the new system using the subset of the benchmark from PRACE consortium. We compare achieved results against the outcomes of the tests performed on clusters based on previous generations of Intel Xeon processors: Intel Xeon E5-2680 (“Sandy Bridge-EP”), Intel Xeon 5680 (“Westmere-EP”) and Intel Xeon 5570 (“Nehalem-EP”) respectively.","PeriodicalId":6469,"journal":{"name":"2014 International Conference on High Performance Computing & Simulation (HPCS)","volume":"5 1","pages":"919-926"},"PeriodicalIF":0.0000,"publicationDate":"2014-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference on High Performance Computing & Simulation (HPCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPCSim.2014.6903787","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In Intel's CPU releasing model, the new Ivy Bridge is a “TICK” that follows Sandy Bridge's (“TOCK”) microarchitecture principles, however, after undergoing a die shrink it is manufactured at 22nm. It also incorporates new micro-architectural upgrades. In this paper we shall evaluate the performance of a 16 bi-socket node cluster based on this 3rd generation Intel Xeon Processor E5-2697v2 meant for server and workstation market. The new architectural improvements are assessed via High Performance Computing Challenge (HPCC) benchmarks and NAS Parallel Benchmarks (NPB) where the interconnect technology is challenged by the standard Intel® MPI Benchmark suite performance evaluator. Finally we tested performance of the new system using the subset of the benchmark from PRACE consortium. We compare achieved results against the outcomes of the tests performed on clusters based on previous generations of Intel Xeon processors: Intel Xeon E5-2680 (“Sandy Bridge-EP”), Intel Xeon 5680 (“Westmere-EP”) and Intel Xeon 5570 (“Nehalem-EP”) respectively.