Design and Implementation of a Low-Power, High-Speed Comparator

Abstract

In the existing world, where demand for portable battery operated devices is increasing, a major push is given towards low power methodologies for high speed applications. Symmetric circuits with regenerative feedback give opportunity to identify new structures that may be particularly useful. Regenerative feedback is usually used in Dynamic Comparators and rarely in non-clocked comparators. Dynamic Comparators are generally used in the design of high-speed Analog to Digital Converters and can easily be designed. The existing comparator requires high accuracy timing Clkb, maximum drive current and high power. To overcome the disadvantages of the existing comparator a new dynamic comparator has been proposed in this paper that uses low power and has less delay. For the performance verification, the design is simulated in Cadence gpdk 180 nm Technology at 1.8 Voltage Supply. Post Layout Simulation results in 180 nm CMOS technology shows that power consumption is reduced by 58% and delay time is reduced by 41%.