{"title":"Comparison of different PLL implementations for frequency estimation and control","authors":"Álvaro Ortega, F. Milano","doi":"10.1109/ICHQP.2018.8378935","DOIUrl":null,"url":null,"abstract":"Accurate and fast-responding Phase-Locked Loops (PLLs) are crucial for the implementation of primary frequency controllers of non-synchronous generation and energy storage devices that are connected to the grid through power electronic converters. PLLs are primarily designed to synchronize a converter to the grid and their ability to estimate frequency deviations is a design-dependent, not necessarily optimized byproduct. The goal of the paper is to establish which design better filters noise and reduces numerical spikes after sudden variations of the voltage at the terminal ac bus of the converter. To this aim, the paper compares five well-assessed PLL implementations through a standard IEEE benchmark system considering both contingencies and noise.","PeriodicalId":6506,"journal":{"name":"2018 18th International Conference on Harmonics and Quality of Power (ICHQP)","volume":"411 1","pages":"1-6"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 18th International Conference on Harmonics and Quality of Power (ICHQP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICHQP.2018.8378935","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 34
Abstract
Accurate and fast-responding Phase-Locked Loops (PLLs) are crucial for the implementation of primary frequency controllers of non-synchronous generation and energy storage devices that are connected to the grid through power electronic converters. PLLs are primarily designed to synchronize a converter to the grid and their ability to estimate frequency deviations is a design-dependent, not necessarily optimized byproduct. The goal of the paper is to establish which design better filters noise and reduces numerical spikes after sudden variations of the voltage at the terminal ac bus of the converter. To this aim, the paper compares five well-assessed PLL implementations through a standard IEEE benchmark system considering both contingencies and noise.