{"title":"Compensation of a winner take all circuit","authors":"G. Kothapalli","doi":"10.1109/ICECS.2003.1302049","DOIUrl":null,"url":null,"abstract":"The design and simulation results of a CMOS winner-take-all (WTA) circuit are presented. A 16-cell test circuit has been designed for intended implementation in an 0.18 /spl mu/m CMOS process. This paper describes the architecture and design issues related to a CMOS WTA circuit. Several design issues such as high resolution, high speed, low power consumption, compactness, and high input voltage range have been addressed. The proposed circuit has a compact configuration of complexity O(N) where N denotes input count. It seems to be very suitable, especially for charge-based applications where input vectors are generated by a set of charged capacitances.","PeriodicalId":36912,"journal":{"name":"Czas Kultury","volume":"54 1","pages":"352-355 Vol.1"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Czas Kultury","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2003.1302049","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Arts and Humanities","Score":null,"Total":0}
引用次数: 1
Abstract
The design and simulation results of a CMOS winner-take-all (WTA) circuit are presented. A 16-cell test circuit has been designed for intended implementation in an 0.18 /spl mu/m CMOS process. This paper describes the architecture and design issues related to a CMOS WTA circuit. Several design issues such as high resolution, high speed, low power consumption, compactness, and high input voltage range have been addressed. The proposed circuit has a compact configuration of complexity O(N) where N denotes input count. It seems to be very suitable, especially for charge-based applications where input vectors are generated by a set of charged capacitances.
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